Browse Prior Art Database

Cache Coherency Protocol minimizing memory write-back operations Disclosure Number: IPCOM000028917D
Original Publication Date: 2004-Jun-08
Included in the Prior Art Database: 2004-Jun-08
Document File: 3 page(s) / 41K

Publishing Venue



A new cache coherency protocol improves the efficiency of multiprocessor cache-based systems by minimizing the accesses to the shared memory for write-back operations. A counter keeps track of how many updated cache line copies reside in the system, so that the write-back operation is triggered only when the last copy is replaced.

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Cache Coherency Protocol minimizing memory write-back operations

Coherent cache protocol with delayed write-back


    Disclosed is a new protocol that reduces the number of write-back operations compared to current protocols such as MTERSI. The main advantage in multiprocessor cache-based systems is that minimal bandwidth is consumed on the shared memory for write-back operations, so that, in systems where processors can communicate through a high-bandwidth medium, the number of processors in the system can be increased.

    The protocol can also apply to software applications for which local inter-process communications are more efficient than communications between a local process and a remote central process.

    In MTERSI protocol, write-back occurs when a T cache line is replaced, disregarding if there is another copy of this modified cache line in another cache.

    Since there can be other copies of the same cache line in other caches, it would be more efficient to defer the write-back operation as much as possible, i.e. when the last copy of the modified cache line is replaced.

    The higher number of processors in the system, the higher the chances is to have other copies of the modified cache line. Considering an extreme example, a cache line read and written frequently by many processors could always be present in at least one of the caches, so that write-back in main memory would never occur, and the cache line would be passed from cache to cache only by intervention.

    The protocol associates a count in addition to states of each cache line: - MCNT: Count of copies of a modified cache line: shows that the cache line has been

updated (not consistent with memory), but also shows how many caches own a copy of this modified cache line.

- R: Recent, shows the most recently accessed cache line (modified or not), used for

selecting the cache source of intervention.

- S: Shared, shows that one or several caches own the same copy of the cache line,

but the cache line is consistent with memory.

- I: Invalid

    The algorithm is summarized below: - Processor Read Miss

(processor references for read a cache line not present in its cache) If another cache has the cache line marked as R:

- The cache line is loaded by intervention from this ca...