Fast High Voltage Level Shifter
Original Publication Date: 2004-Jul-25
Included in the Prior Art Database: 2004-Jul-25
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The following text presents an idea which provides an improved voltage level shifter for a fast logic level translation without increasing circuit complexity and current consumption. Fig. 1 shows a standard DC level shifter, generally used for such low quiescent current application. A logic signal from the low voltage rails VSS and VDD is transferred to a translated switching signal disposed between the VSSH and VDDH rails. As illustrated in the next picture, Fig. 2 (left and right), the translation delays depend mainly on the charging-discharging time of the parasitic capacitors. An increment of the N1-2 size, in order to improve the corresponding transconductance, can optimize the switch from H to L. As a result, the related drain to substrate parasitic capacitor C3 increases, slowing down the other transition L to H.