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Process Test at Silicon Level, or Package and Silicon, in the Same Tester Module Footprint

IP.com Disclosure Number: IPCOM000029145D
Publication Date: 2004-Jun-16

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for manipulating a test head to a wafer test application, or a package and silicon application, all contained within a single tester footprint. Benefits include reducing product development time.