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A method for increasing the quality of system-level interconnect test-cases Disclosure Number: IPCOM000029262D
Original Publication Date: 2004-Jun-21
Included in the Prior Art Database: 2004-Jun-21
Document File: 4 page(s) / 143K

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This invention deals with a mechanism that improves the quality of system level test-cases. This mechanism aims at gaining better stimulation of both the system’s resources and its interconnect.

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A method for increasing the quality of system -level interconnect test-cases

Functional verification is widely acknowledged as the bottleneck of a hardware design cycle (See "Writing Testbenches: Functional Verification of HDL Models", Janick Bergeron, Kluwer Academic Publishers, January 2000). Simulation is the main functional verification vehicle for large and complex designs, and, therefore, stimuli generation plays a central role in this field. The generated stimuli, usually in the form of test-cases, are designed to trigger architecture and micro-architecture events defined by a verification plan.

    The input for a test-case generator is a specification of a test template, for example, tests that exercise the data cache of the processor and that are formed by a series of double-word store and load instructions. The generator generates a large number of distinct, well distributed test program instances that comply with the user's specification. The variation among different instances is achieved through a large number of random decisions made during the generation process.

    Generated test programs must meet two inherent classes of requirements: (a) Tests must be valid. That is, their behavior should be well defined by the specification of the verified system. (b) Test programs should also be of high quality, in the sense that they expand the coverage of the verified system and focus on potential bugs.

    A hardware system can be viewed as comprised of two complimentary layers: A set of resources, either computational (processors, DSPs, co-processors), memory related (memories, caches), I/O, or other
(e.g., DMA engines). Many systems and SoCs (Systems on a Chip) contain multiple instances of the same type of resource - multiple processors, multiple memories, multiple I/O devices, and so forth. A layer of interconnect between these resources is used to transfer information among them. A system bus is a simple and commonly used type of interconnect. Modern system architecture typically uses more complex, network-based interconnect mechanisms. These may contain bus-bridges, hubs, switches, etc.

    The verification of systems is done using test-cases that are comprised of a set of transactions. Several resources, as well as the part of the interconnect used for the communication among these resources, are stimulated by a transaction. Transaction examples are a processor accessing a certain memory location, or a processor initiating an inter-processor-interrupt to another processor, by notifying the system's interrupt controller.

    A transaction is usually initiated by instructing one of the resources of the system to approach another resource. In the processor and memory example, this would be done by executing a store or a load assembly instruction on the processor. This leads to the common practice in which test-case generation is centered at the resources of the system, and not on its interconnect.

    This invention deals with a mechanism tha...