Run-time Failure Analysis Circuit for Autonomic Computing Systems
Original Publication Date: 2004-Aug-25
Included in the Prior Art Database: 2004-Aug-25
A method is shown in which memory failures may be more accurately and efficiently diagnosed. This technique allows for either software or hardware to map failures in a novel way that is both efficient and comprehensively maintains failure information. The information can be used in turn to aid in failure diagnostics, array repair during manufacturing, or in array repair in field applications.