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Setup and Hold Measurement Procedure for Laser Diode Drivers with integrated Write Strategy Generation Disclosure Number: IPCOM000030854D
Publication Date: 2004-Aug-30
Document File: 3 page(s) / 55K

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The Prior Art Database



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Setup and Hold Measurement Procedure for Laser Diode Drivers with integrated Write Strategy Generation

This document describes a setup and hold measurement procedure that is applicable for Laser Diode Driver (LDD) components with an integrated Write Strategy Generator (WSG).

The measurement procedure does not require expensive measurement equipment with extreme requirements on timing resolution. It is therefore suitable to be used in automated measurements in IC production test facilities as well.

A Laser Diode Driver with an integrated Write Strategy Generator function transforms channel-code input symbols, either Eight-to-Fourteen (EFM) codes or 1-7 codes for blue laser systems, into pulsed currents to drive laser diodes.

Typically LDDs with integrated WSG have the ability to transform channel-code symbols with specific lengths using separate timing parameters. They even have the possibility not to transform channel-code symbols of specific length.

The procedure described in this document makes use of that property of the LDD component.

Setup and hold parameters relate to the ability of the LDD component to correctly clock in the EFM or 1-7 channel-code symbols before further processing takes place.

Typically clocking in of channel-code symbols is not done using the channel clock signal received from an encoder directly. Instead of that the channel clock signal received from the encoder serves as input signal for a Phase Locked Loop (PLL) or Delay Locked Loop (DLL) that regenerates the channel clock signal. The regenerated clock is then used to clock in (or retime) the channel-code symbols received from the encoder.

The figure below depicts a typical block-diagram of an LDD with integrated Write Strategy Generator mounted on an Optical Pickup unit.




  + Laser Current





Channel Encoder

EFM/1-7 Data

Channel Clock

OPU: Optical Pickup Unit LDD: Laser Diode Driver WSG: Write Strategy Generator PLL: Phase Locked Loop LVDS: Low Voltage Differential Signaling SE: Single-Ended

The PLL/DLL makes characterization of setup and hold parameters of an LDD more complex then characterizing setup and hold for a simple flip-flop element. Especially at low channel clock frequencies setup and hold parameters of the LDD will be dominated by PLL jitter.

Setup and hold parameters of the LDD are also influenced by a second mechanism. Typically the channel clock and the channel-code symbols are transferred from encoder to LDD using LVDS signaling.

The LDD converts the LVDS signals into Single-Ended signals before further processing will take place.

In practice this conversion is not perfect, it will affect the channel-code symbol length with a small amount (in the order of tenths or hundreds of picoseconds).

This effect length reduction or stretching will also affect setup and hold parameters of the LDD.

20 August, 2004


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Violations of setup and/...