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Method for Guaranteeing Correct Output of Non-Power of 2 Entry Register File

IP.com Disclosure Number: IPCOM000030873D
Original Publication Date: 2004-Aug-31
Included in the Prior Art Database: 2004-Aug-31

Publishing Venue

IBM

Abstract

A method of guaranteeing correct output for non-power-of-2-entry register files is disclosed. If a typical decoder is used to decode the addresses of these family of register files, it is likely that some address combinations will not decode to a physical address. The solution shown in this article efficiently detects cases where an address would have caused floating outputs and ensures that the outputs do not float. Also, an efficient algorithm is given for the detector, which takes advantage of a special pattern that occurs when one tries to minimize the logic for the detect function. Finally, a method for saving further logic and time by sharing decoder logic with the detection logic is shown. The method can be implemented without significantly modifying typical register file design-concepts.