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Caches that support QoS

IP.com Disclosure Number: IPCOM000031029D
Original Publication Date: 2004-Sep-07
Included in the Prior Art Database: 2004-Sep-07

Publishing Venue

IBM

Abstract

Most caches today have a Set Associative architecture (meaning they are built of "X-ways" sets, typically X=4 or X=8 at L2 caches); this is designed to utilize the cache size. The idea presented herein uses this existing mechanism to ensure minimal resources to groups of threads (or other cache clients).