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FinFET Compatible, 3 Dimensional Capacitor

IP.com Disclosure Number: IPCOM000031168D
Original Publication Date: 2004-Sep-15
Included in the Prior Art Database: 2004-Sep-15

Publishing Venue

IBM

Abstract

An optimized physical layout is defined that limits capacitor series resistance while maximizing capacitive density for finFET technologies. Variations in length and width of the optimal capacitor will result in several possible implementations as the fin height, fin pitch, gate material, and silicon resistance change.