FinFET Compatible, 3 Dimensional Capacitor
Original Publication Date: 2004-Sep-15
Included in the Prior Art Database: 2004-Sep-15
An optimized physical layout is defined that limits capacitor series resistance while maximizing capacitive density for finFET technologies. Variations in length and width of the optimal capacitor will result in several possible implementations as the fin height, fin pitch, gate material, and silicon resistance change.