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Cache line fetch data integrity test algorithm

IP.com Disclosure Number: IPCOM000031319D
Original Publication Date: 2004-Sep-21
Included in the Prior Art Database: 2004-Sep-21

Publishing Venue

IBM

Abstract

Current memory tests typically rely on write-read-compare operation to verify the data integrity of both the memory and the cache subsystems. When testing strictly memory, there are various addressing algorithms which bypass the cache, but the basic mechanism of analyzing forced memory fetches at particular address remains the same. In one system under development, it was noticed that these conventional memory tests would fail to report data miscompares even in systems where it was known that such failures had occurred. It was determined that, due to the inherent cacheline architecture of the memory controller, the location that a given memory error occured was beyond the address actually being analyzed. A new test was required for two main reasons: First in modern memory architectures which fill whole cachelines per fetch, simply analyzing a single data item ignored other data items from the fetch that could have failed. Simply reading all the addresses can mask the problem due to the excessive overhead of memory operations. Also, the affected data locations can often be behind (address-wise) the current address, so they would be missed in a normal sequential read. A second need for an improved test is the ability to verify the accuracy of a reported error in hardware and reporting the details of the failure correctly (when ECC is turned off). For these reasons, a new test was developed which integrated the fetching mechanisms of the memory controller into the analysis logic.