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Voltage Supply Threshold Detector Disclosure Number: IPCOM000031455D
Original Publication Date: 2004-Oct-25
Included in the Prior Art Database: 2004-Oct-25

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When an electronic device is powered up, the internal circuitries can assume different initial states. Often parasitic elements determine the states after the power-on. For assuring that circuitries assume a defined initial state, generally a 'Power On Reset'-signal is required. Additionally, a reset signal typically exists for keeping the digital units in a reset state until the power line exceeds a predetermined threshold voltage. For many cases, like Power MOS driving, an internal voltage monitoring apparatus is mandatory to avoid an irreversible damage to the application circuit. In Figure 1 a typical use case is depicted, a high speed driver with bootstrapping for dual power MOSFETs. Figure 2 shows the main structure of the bias unit, which generates all the internal voltage supplies and a logic level signal (ENAble). Essentially the TGATE and BGATE are turned off until ENA is low. If at the startup Vcc increases abruptly, the sensing point at the R1-R2 resistor divider might ramp up faster than the band gap voltage reference (as a consequence of the internal setting time). As a result, a wrong enable signal may cause the driving stage to switch on, although the nominal current and voltage supplies are not yet reached, leaving the device in an undefined and potentially dangerous state. Therefore, usually an 'AND'-combination of the battery sense detector output (UV) and the internal 'Power On RESET'-signal (RESET) of the avdd bias (analog supply) is introduced, which then provides the general reset signal for the whole system. Thus, the 'AND'-combination of the two signals avoids the triggering of a false ENA-signal during fast input voltage transition at the power on/off. As illustrated in Figure 3, the RESET does not release any signal before the analog voltage supply crosses the 4.1V threshold.