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Isolation Trench Fills with High Aspect Ratios in FEOL Applications

IP.com Disclosure Number: IPCOM000031456D
Original Publication Date: 2004-Oct-25
Included in the Prior Art Database: 2004-Oct-25

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Advanced low-k technologies are rapidly approaching production maturity for logic and most recently DRAM products. In addition to a low dielectric constant, many low-k material processes exhibit excellent gapfill behavior because they are mostly deposited as liquids (e.g. spin-on, CVD condensation processes). Such a property makes low-k very attractive for high-aspect ratio structures if temporary or permanent fill functions have to be addressed. State of the art fills are done with HDP (High Density Plasma) or conformal deposition processes like LPTEOS (Low Pressure TEOS). These processes result all in fill voids or seams at the surface. Beside the void free fill the material properties like film stress need to be carefully controlled. Films with high tensile stress lead to cracking of the IT (Isolation Trench) structures. This becomes more serious for the future because the structures become smaller and more sensitive to mechanical deformation. A new integration flow for SGT (Surrounding Gate Transistor) process is proposed. The integration flow offers a possibility to integrate fill processes like low k flow fill or SOG (Spin on Glas) into the FEOL (Front End of Line) processing. Especially it involves dielectrics with a lower dielectric constants as silicon oxide as fill materials for trenches with high aspect ratios and negative taper angles.