Signal redistribution structure on single center pad row memory chips reducing signal loop inductance
Original Publication Date: 2004-Nov-25
Included in the Prior Art Database: 2004-Nov-25
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The following concerns about stacked FBGA (Fine-pitch Ball Grid Array) memory technology in an attractive package solution in cases when higher memory density at the same footprint is required, but single chip solutions are either not yet available or they have low yield and higher cost. The fulfillment of electrical performance specifications in stacking solutions is a fundamental concern. The overall conductor line inductance for stacked solutions may become critical, as well as inductance matching for bottom and upper chip signal paths, especially in the case of over-the-edge stacking solutions, where z-axis connection over the chip's edge is required (Fig. 1). There is one metal layer to be used for signal rerouting from chip pad to chip's edge. Either electroplated copper or sputtered aluminium can be used for this purpose. The lack of a reference plane for the signals routed on chip will force the currents to use dedicated power/ground traces or displacement capacitances M2 traces - redistribution layer as a return path (Fig. 2). In the case when power/ground traces are not adjacent to the signal, the result will be a highly inductive signal path on chip and inductance mismatch for different signals. Upper chip interconnects may have inductances up to 9nH depending on the design type and chip size. The issue may not allow the usage of the stacking solution at higher clock frequencies.