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Weighed Interpolating Alignment Correction

IP.com Disclosure Number: IPCOM000032845D
Original Publication Date: 2004-Dec-25
Included in the Prior Art Database: 2004-Dec-25

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Abstract

Deep trench isolation in integrated circuit technology offers several advantages that can be exploited indifferent applications. For example, in bipolar and BiCMOS technologies they are used to improve performance by reducing the device parasitics. Trenches are etched using an appropriate hard mask. Erosion of this mask may cause physical wafer deformation. This distorts the die grid printed in deep trench and will, if not corrected, give an overlay error between the deep trench layer and all subsequent layers. The error will be measured by both the overlay measurement and the wafer alignment of the exposure tool, but at present, both are unable to correct for higher order deformations. At present the alignment model of the exposure systems corrects 4-6 parameters at wafer level: • Translation X, Y • Wafer scaling X, Y (grid magnification X, Y) • Wafer rotation and non-orthogonality (grid rotation X, Y) Physical deformations of these parameters can entirely be removed. Furthermore, static high order deformations (not varying over wafers) could in principle be corrected by die dependant process corrections at the exposure tool. These models have no possibility at all to correct for higher order wafer grid distortions that differ from wafer to wafer, i.e. due to non optimized or non stable previous process steps.