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Disabled Interrupt Processing Model with Deferred Execution Disclosure Number: IPCOM000033027D
Original Publication Date: 2004-Nov-22
Included in the Prior Art Database: 2004-Nov-22

Publishing Venue



Platforms such as Power use a priority interrupt model that allows the operating system (AIX) to disable interrupts at or below a given priority while still permitting interrupts above that given priority. Within this model, the operating system can defer certain activities such as specific classes of I/O completion processing, until the thread's interrupt priority is set to some lower interrupt priority. This article describes a method to model this hardware/operating system behavior in the absence of the actual hardware supported capabilities, specifically to provide the correct I/O completion semantics expected by AIX device drivers.