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Counter Synchronization Disclosure Number: IPCOM000033040D
Original Publication Date: 2004-Nov-22
Included in the Prior Art Database: 2004-Nov-22
Document File: 1 page(s) / 50K

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Counter synchronisation between two clock domains

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Counter Synchronization

In most of the ASIC of today there are multiple clock used, with some of them asynchronous. There is always a problem when data are passed from a clock domain to another one.

This invention relates to counter synchronization.

In some specific application, there are events that are counted in one clock domain, and this information has to be used in a different clock domain.

For instance, a counter that counts the number of error is used at some critical fast logic, but the status is done through a microprocessor at a lower speed.

Usual method: The usual method used in such a case is to use a large enough counter on the fast speed to count all the events.

The count number is then given to the slow speed logic using either a hand check mechanism or a gray counter synchronization mechanism.

This lead to two things: having a large counter used on a fast logic, hence having potential timing problems and power dissipation.

The proposed method: There are many application that don't really need the exact count amount. In this applications, a quantification error can be tolerated.

In this cases, a very small counter of 3 bits can be implemented in the fast speed logic.

This counter will wrap every time it has reached its limit. The MSB of the counter, will vary every 4 clock cycles of the fast clock.

This signal is slow enough to be used on the slow speed logic. (This is an example, if there is a bigger clock ratio, the counter has to be larger, if...