Extension of a Standard Processor to Improve Bit-field Manipulation Capabilities
Original Publication Date: 2004-Dec-25
Included in the Prior Art Database: 2004-Dec-25
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Generally, communication/networking protocols need to extract, analyze and modify bit-fields. Bit-fields are neighboring multi-bit information within a 16 or 32 bit word, usually carrying specific parameters, such as types, indicators, lengths or addresses. The size of bit-fields can range from one bit to several bytes. Standard processors are capable of handling data of fixed size e.g. 64 bits, some with scalable options of 8/16/32/... They are by nature very cumbersome with sizes like 2, 4, 12, ... which are the common bit-field sizes. For example: If a 32-bit processor wants to modify 12 bits of a 32 bit data it must perform memory read, multiple shifting, several masking operations (in the form of OR/AND) and then writes the modified 32-bit data back to the memory. These operations take several cycles and that degrades the system performance. In addition, these instructions occupy memory space, which is precious in SoCs (Systems on a Chip). Up to now, there are two solutions - pure hardware protocol processing engines and proprietary/in-house processors. In the first solution, the protocol is first analyzed and then the architecture is derived. When implemented in hardware, there will be heavy restrictions on bit-wise access or they might not even exist. The second proposal is to build a proprietary processor that will support bit-field oriented instructions. This may include bit-field extraction, masking, repositioning, bit-wise accesses to external memories and so on. Both solutions have some disadvantages and restrictions, and consume additional cost and time to develop.