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Cost Effective Stacking and Electrical Interconnection of IC Chips

IP.com Disclosure Number: IPCOM000033115D
Original Publication Date: 2004-Dec-25
Included in the Prior Art Database: 2004-Dec-25

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Abstract

Three-dimensional integration is a rapidly emerging technology that promises to provide substantial benefits in IC functionality and cost in a smaller, more efficient package. A wide variety of heterogeneous technologies can be integrated with this technique, including logic, memory, analog circuits, and sensor/detector technologies. Up to now, neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. Then, the same-size neo-chips can be efficiently stacked using well-developed processing steps.