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FRACTIONAL-N PLL AND A PROGRAMMABLE MODULATOR TO ACHIEVE EMI REDUCTION THROUGH CLOCK DITHERING

IP.com Disclosure Number: IPCOM000033131D
Original Publication Date: 2004-Nov-29
Included in the Prior Art Database: 2004-Nov-29

Publishing Venue

Motorola

Related People

Authors:
Christopher M. Tippett

Abstract

This paper describes using a fractional-N PLL and a programmable modulator component to achieve EMI reduction through clock dithering. Fractional-N PLL's employ a known technique to allow a PLL to lock onto a fractional frequency, and use a delta-sigma filter to remove unwanted noise harmonics. The bandwidth of the PLL is higher than some other methods, such that the PLL can slew to a new frequency much faster. The modulator component controls the set point of the fractional-N PLL. Through the digital logic or a ROM in the modulator, the set point of the PLL can be stepped to a new set point, causing the PLL to slew to the new set point. Since the fractional-N technique allows the PLL to lock to fractional frequencies, the modulator can step the output frequency in very small increments, unlike competing ideas with a fixed prescaler divider. With the modulator able to step through frequencies in small increments, the modulator can create any desired clock frequency modulation waveform. In addition, the modulation rate can be set at any frequency within wide range of modulation frequencies. The control of the modulation waveform and modulation rate can be done through software programming of the modulator component.