Kerf design and process interaction to improve chip defect density
Original Publication Date: 2004-Dec-07
Included in the Prior Art Database: 2004-Dec-07
The removal and suppression of defects is critical for achieving the yield requirements of 0.13um embedded DRAM (eDRAM) products. During the formation of the deep trench (DT) capacitors, non-ideal lithography and etching cause fragile pillars to form on the edge of the wafer. These pillars are easily broken off during subsequent processing and become defects on the surface of the wafer. The remaining pillars on the edge and the bevel of the wafer also trap surface fm during subsequent processing. Disclosed is a process whereby adjusting the kerf DT fill pattern density, the printing of pillars is suppressed, and the generation of defects due to this mechanism is eliminated.