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A Method and Circuit for Self Tuning of Setup and Hold Margins for Embedded Memory Devices Disclosure Number: IPCOM000033399D
Original Publication Date: 2004-Dec-09
Included in the Prior Art Database: 2004-Dec-09
Document File: 3 page(s) / 227K

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This paper discloses a circuit and method for self-test and self-repair of signals relative to setup and hold specifications. This circuit and method apply to either the external inputs and or outputs (I/O) of a chip, or the internal I/O between functional units of a system-on-chip (SOC).

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A Method and Circuit for Self Tuning of Setup and Hold Margins for Embedded Memory Devices

As chip speeds continue to increase faster then external test system speeds, guaranteeing external setup and hold specifications is difficult. Even more of an insidious problem is designing internal setup and hold timings correctly as deep sub-micron modeling of transistors and parasitic delays becomes subject to more error (particularly early in a technologies life cycle). These difficulties are the force behind the desire to solve the problem internal to the chip.

The scope of this internal solution is not a design methodology paradigm shift; rather, it is an enhancement in general to built-in self-test (BIST) methodology. Whereas, BIST methodology typically focuses on functional test and repair of complex macros (typically memories), this self-test and self-repair circuit and BIST methodology enhancement embody a movement to the addition of margin tests for setup and hold timings (an area not normally covered by BIST) to the overall BIST methodology. In addition to guaranteeing that a macro or chip meets a timing specification, the use of this solution helps aid in the creation of first-time-right designs, without the worry of failed setup and hold timings between macros in a SOC design looming over early hardware.

The self-test and self-repair circuit that is disclosed here pertains to an area where much work has been done to accomplish setup and hold margin test. An example application is in an embedded memory device with a remote BIST circuit. The self-test and self-repair circuit guarantees the embedded device's input and output to the BIST . Figure 1 shows how this circuit fits in between the BIST and the embedded device.

Figure 1: System Block Diagram

The self-test, self-repair setup and hold circuit consists primarily of a state machine, delay mechanism, processing logic, state registers, electrical fuses, and a redundancy engine for comparing the received data with the expected data. The above circuits are reusable for each instance of the circuit, except for the delay mechanism and electrical fuses, see figure 2. Figure 2: Circuit Block Diagram


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The state machine governs the system. Once enabled, this state machine increments a counter after each test of the memory. The counter changes the setting of a variable delay circuit. An I/O line passes through the variable delay circuit. When the test begins, the counter has set the delay circuit to its slowest setting....