Method to Statically Classify Clock-signal Behavior for the Verification of Clock-Control Functionality and Distribution on a Microchip Design.
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
Disclosed is a method and system for automatically classifying clock signals in a design under verification. These classifications imply a set of predicted behaviors for the clock signals that may be automatically checked using simulation or formal analysis.
Method to Statically Classify Clock -signal Behavior for the Verification of Clock -Control Functionality and Distribution on a Microchip Design .
Disclosed is a method and system for automatically classifying clock signals in a design under verification. These classifications imply a set of predicted behaviors for the clock signals that may be automatically checked using simulation or formal analysis, rendering a fully automatic and powerful overall solution for verifying the clocking logic of sequential designs.
The specified behavior of clocks and clock control functionality in a sequential design need to be compared with the actual behavior of those elements in the hardware implementation. In order to make such a comparison, it is required that a specification is made for every clock signal in the design under verification (DUV). As clock signals may be added or removed with each revision of the DUV, and since a DUV may implement tens of thousands to millions of distinct clock signals, manual specification is not feasible. An automated method to specify the behavior of each clock signal is necessary.
An iterative process is used to analyze the design implementation description in order to create classifications for every clock signal in the design. These classifications constitute specifications, which are used to predict the expected behavior of each of the clock signals. The behavior of the design implementation is then automatically validated to adhere to these specifications using simulation or formal analysis. The classification is performed as follows.
A software toolset parses the design description to examine every logic device implemented in the design. If an examined device is found...