Self-Identifying CPU and Bus Structures
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
This article will present a self-identification method for use in logic simulation models. The method is used for complex multi-core or multi-bus System-on-Chip (SoC) and ASIC designs running in an event simulation environment. The approach is currently used in IBM's System-on-Chip platform based design kits.