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Methodology for Automated Error Free OP Resistor Insertion Disclosure Number: IPCOM000033529D
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
Document File: 3 page(s) / 34K

Publishing Venue



Automated methodology that produces error free dynamic output impedance matching for IO circuits based on circuit attributes defined in a IP database and extracted chip parasitics.

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Methodology for Automated Error Free OP Resistor Insertion


IBM ASIC chip methodology has built -in provision for dynamically matching IO circuit output impedance to the extracted line resistance from the IO output through chip and package wiring . This is known within IBM ASICs as OP(or BR) Insertion, and is currently accomplished via a program that determines the correct OP/BR resistor to be inserted into each IO on the chip based on information in a technology specific design system input file called the technology PDL and a PAD Pin CLASS keyword that is coded in a circuit abstract model called a VIM DEF.

The current process requires the IO VIM DEF developer to manually determine and enter the Technology PDL constructs and IO VIM DEF CLASS keywords that are used by the OP insertion program.

The Technology PDL is the center of all design system function, and should not be subject to revision each time an OP pluggable IO is added to the product offering. The manual nature of VIM DEF and Technology PDL edits for OP insertion support is a rules quality concern that impacts customer satisfaction and creates back level rule versioning concerns.


Disclosed is a new OP insertion methodology which utilizes a completely new OP insertion program and rules construction/configuration(IO VIM DEF, Technology PDL) methodology, and will take advantage of automation with respect to VIM DEF generation and a new OP insertion algorithm that take IO circuit attributes defined by the IO developer in an IP database.

The new methodology uses a static set of predefined tec...