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A method for enhancing the manufacturability and signal integrity of VLSI designs.

IP.com Disclosure Number: IPCOM000033532D
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14

Publishing Venue

IBM

Abstract

We present a method for enhancing the manufacturability and reliability of vias in a VLSI layout by adding redundant vias and metal borders.