Method for I/O Impedance Matching For Differential I/O Circuits
Original Publication Date: 2004-Dec-14
Included in the Prior Art Database: 2004-Dec-14
A method to identify and check differential PAD/PADN pins on differential I/O books which require precise pluggable resistors to minimize resistance variation. The method would be used in checking tools, circuit placement tools and detailed wiring tools.
Method for I/O Impedance Matching For Differential I /O Circuits
The steps needed for identifying the differential PAD/PADN pins is to annotate the differential I/O books DEF's with keywords thus identifying them to CAD tools. This identification alerts the CAD tool to the fact that the PAD and PADN pins need strict balancing. Chip designers also would be allowed to update the chip designs with keywords to add restrictions to any I/O books which do not already support the strict resistance balancing.
The following flow represents the preferred embodiment: place the I/O books
route the I/O book's PAD and PADN books up to their respective package pins
perform resistance extraction on the detailed wires and package resistance for both
the PAD and PADN book calculate the BR/OP resistor size using the following formula:
Target Resistance - ((Net Resistance + Package Resistance + Module Resistance) + Impedance) = Ideal BR/OP Resistor Size Using the Ideal BR/OP Resistor Size, find the best matching BR/OP Resistor from
the released technology library the resistors are generally, in IBM technologies, in 2 Ohm increments, however the process allows for arbitrary non-uniform increments Compare the selected resistor sizes for the PAD and PADN books
if the resistors match, continue (ARRAY C4 images): if the resistors differ, calculate the difference and either report it back to the engineer or directly to a router to have the net rerouted using new net const...