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Digital Signal Assist Circuitry ( D.S.A.C) Disclosure Number: IPCOM000033633D
Original Publication Date: 2004-Dec-20
Included in the Prior Art Database: 2004-Dec-20
Document File: 2 page(s) / 39K

Publishing Venue



Poor slew rates on long wires ( global interconnects, word-lines) is a predominant problem in today's integrated circuits. Having good slews improves gate drive, noise immunity and allows for faster circuit operation. Digital Signal Assist Circuitry (DSAC) addresses this problem by incorporating a small footprint circuit which actively improves the slew rate of signals. Existing solutions for poor slews include rebuffering, word-line boosting and hierarchical word-line architecture(s). These existing solutions have draw backs such as increased latency/delay in the signal, increased area/interconnect usage, or complex circuit overhead . DSAC provides a simple solution to poor slew rates in critical circuits.

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Digital Signal Assist Circuitry ( D.S.A.C)

Disclosed is a set of circuits known as Digital Signal Assist Circuitry DSAC. The main idea behind DSAC is to use a pulsed keeper to "assist" in pulling up or down a signal. DSAC is intented for use on long wires(with or without distributed loads) with bad input and output slew rate(s). There are 2 basic variations of DSAC circuits. The first implementation is designed to improve slew on the rising edge of the signal while the second variation is designed to improve the slew of falling edge of the signal.

The rise implementation:

This circuit implementation comprises of 3 parts: an odd delay chain, a nand gate and a pfet. The primary goal of the odd delay chain coupled with the nand gate is to generate a pulsed signal to the pfet based on the rise of the signal whose slew is being improved. The nand gate is skewed towards the nfet so as to lower the switching threshold of the gate therby making the transition speedier. The falling edge of the resulting pulse then turns on the pfet helping pull up the signal faster. The rising edge of the pulse then turns off the pfet once the signal has been brought to rail. The width of the pulse is determined by the amount of delay in the odd inverter chain. the reason for using a pulsed circuit is to avoid "fighting" on the fall cycle of the path.

The fall implementation:

The fall implementation is similar to the rise implementation with the exception of the nand gate.

The nand gate i...