Method and Apparatus to Reduce Test Time and Test Cost When Acquiring High Volumes of Frequency Measurements on VLSI Chips
Original Publication Date: 2004-Dec-20
Included in the Prior Art Database: 2004-Dec-20
This invention describes an efficient method for measuring frequency in parallel on multiple frequency sources on a VLSI chip. This invention reduces frequency measurement test cost by reducing test time and by eliminating need for external frequency counters or oscilloscopes. This technique reduced test time by utilizing two methods. First, it reduced test time by providing a method for measuring frequency in parallel at all on-chip frequency sources at the same time. Second, it reduced test time by measuring frequency at speed. Test cost is reduced by moving frequency measurement complexity onto the chip. Frequency counters can be built on chip at the output of every frequency source. By building frequency measurement devices on chip, the need for external frequency measurement devices is eliminated. All what is needed is a basic primitive tester of PC interface card.