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Method and Apparatus to Reduce Test Time and Test Cost When Acquiring High Volumes of Frequency Measurements on VLSI Chips Disclosure Number: IPCOM000033634D
Original Publication Date: 2004-Dec-20
Included in the Prior Art Database: 2004-Dec-20
Document File: 4 page(s) / 56K

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This invention describes an efficient method for measuring frequency in parallel on multiple frequency sources on a VLSI chip. This invention reduces frequency measurement test cost by reducing test time and by eliminating need for external frequency counters or oscilloscopes. This technique reduced test time by utilizing two methods. First, it reduced test time by providing a method for measuring frequency in parallel at all on-chip frequency sources at the same time. Second, it reduced test time by measuring frequency at speed. Test cost is reduced by moving frequency measurement complexity onto the chip. Frequency counters can be built on chip at the output of every frequency source. By building frequency measurement devices on chip, the need for external frequency measurement devices is eliminated. All what is needed is a basic primitive tester of PC interface card.

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Method and Apparatus to Reduce Test Time and Test Cost When Acquiring High Volumes of Frequency Measurements on VLSI Chips

This invention describes a method and an apparatus. This invention provides a high level description of an on chip frequency counting device. It describes frequency measurement method that utilizes the described apparatus on VLSI chips.

The on chip frequency counting devices are called: On Chip Frequency Measurement Units or (OCFMU). These devices utilize n-bit binary counters that use the external reference signal REF as a timing signal.

All OCFMU are configured into scan shift registers during scan mode. All OCFMU are connected to chip level scan chains. The frequency count (COUNT) can be downloaded into the tester using scan chains.

Description of OCFMU:

The On Chip Frequency Measurement Unit (OCFMU) described in Fig. 1 serves as an on chip frequency counter. OCFMU comprises a binary counter and control logic. The counter in OCFMU is incrimented by on every rising edge on the OSC input while REF and ENABLE are active and CLR is inactive. To use this device as a frequency measurement device an external reference signal, REF, with a know duration T must be activated while ENABLE is active. During the time "T", the oscillating signal at OSC increments the counter a number of times. The number of increments, COUNT, is saved in the counter flip flops. To calculate the oscillating signal frequency, the count value, COUNT, is divided by the REF signal pulse duration:


The value in OCFMU is cleared to "0" using the clear signal CLR. OCFMU is cleared to "0"s on the rising edge of CLR while ENABLE is active.

The high level description of OCFMU is shown in Fig. 1(a) and the timing diagram is shown in Fig. 1(b).

The flip flops in OCFMU must be connected in a scan shift register configuration. The scan input is SI and the scan output is SO. The shift clock (S. CLK) shifts the bits in the flip flops during the scan mode.


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       SI OSC




(n-bit binary counter)






(a) High level description







0 1 2 3 4 5 6 . .

(b) Timing Diagram


Fig. 1: On Chip Frequency Measurement Unit (OCFMU)

The drawing in Fig. 2 describes the implementation of the invention on a VLSI chip. Frequency sources are connected to OCFMU units on a VLSI chip. The chip is controlled by a test apparatus (Tester) through a probe set in...