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Circuit Contention Free Scan Testing

IP.com Disclosure Number: IPCOM000033784D
Publication Date: 2004-Dec-28

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that enables VLSI design circuits with full scan designs to operate contention-free during scan testing, thereby making them automatic test generation program (ATPG) and Logic-BIST friendly. Benefits include improving and simplifying testing.