Method for an enhanced tag correction mechanism for ECC-protected caches

Method for an enhanced tag correction mechanism for ECC-protected caches

Disclosed is a method for an enhanced tag correction mechanism for error correction code (ECC) protected caches. Benefits include improved functionality and improved performance.

Background

              Conventional processor caches are designed with ECC protection for the tag array. The occurrence of tag errors is rare, and multiple tag errors within same set even rarer. Processors use error correction circuitry for all the many ways (k-ways) of set-associative cache.

              A conventional k-way set-associative cache with support for ECC error detection and correction requires many, designated as k, sets of logic. They are required for a parallel tag look-up mechanism. In some implementations, the ECC logic can incur extensive processing overhead. In this case, the implementation enters a tag error-scrubbing loop at error detection to correct all the faulty tags. However, this mechanism is not lockstep friendly. To overcome this drawback, two processors are used in a redundant configuration to execute the same code at the same time regardless of correctable errors.

General description

              The disclosed method uses one set of ECC logic that is lockstep friendly. In the rare event of multiple tag errors in a set, the cache enters an error scrubbing mode and breaks lockstep.

              The disclosed method can be adapted to include multiple sets of ECC logic.

Advantages

              The disclosed method provides advantages, including:

•             Improved functionality due to providing a lockstep-friendly ECC function

•             Improved functionality due to providing an error-scrubbing mode for multiple errors and non-lockstep applications

•             Improved functionality due to providing ECC using a reduced number of logic sets

•             Improved performance due to using a single set or a reduced number of sets of tag ECC correction logic

Detailed description

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