Memory Controller Managed Backing of Superpages
Original Publication Date: 2005-Jan-06
Included in the Prior Art Database: 2005-Jan-06
As the working set of virtual pages required by application software grows, so does the miss rates for translation look-a-side buffers (TLB) used to managed virtual to physical page address mapping. One method of reducing this TLB miss rate is to increase the size of virtual pages, allowing the TLB to map a greater span of virtual to physical translations at any given time. Increasing the virtual page size has other side effects too, such as reducing the efficiency of physical memory usage and increasing the response time for establishing new pages in memory. Both of these issues can be addressed by inserting another virtual addressing layer in between the processor's virtual to physical mapping, and allowing the memory controller to perform this secondary virtual to physical address translation.