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Mechanism To Provide Internal Bypass In A Register File With Low Circuit Overhead Disclosure Number: IPCOM000033986D
Original Publication Date: 2005-Jan-10
Included in the Prior Art Database: 2005-Jan-10
Document File: 3 page(s) / 64K

Publishing Venue



A method of employing an extra-leg in the alignment multiplexer to provide data bypass inside an instruction buffer register file array is disclosed.

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Mechanism To Provide Internal Bypass In A Register File With Low Circuit Overhead

A register file array is a group of single memory element (SRAM). This single memory cell can be single ported (one read and one write) or can be multi-ported read and write. To eliminate the complexity of large number of read/write ports (e.g., 8 write and 5 read), it has sometimes been proven more efficient to divide the data into a number of groups (e.g., 8 groups) with single read and write ports. The data coming from instruction cache (icache) is rotated and then stored in the ibuf, because, icache data contains both valid and invalid values. But the data remains unaligned as the data starts to occupy from the first empty slot. The read-out data from ibuf needs to be aligned before it can be used in the next cycle. At the same time, these data need to be multiplexed with the original but aligned data coming out of the icache, based upon whether bypass is needed or not. All these functions are implemented inside the register file array. Because of 8 simultaneous instructions written into ibuf in one cycle, the alignment of incoming data is essentially an 8:1 multiplexer, the alignment of ibuf read-out data and internal bypassing is another 9:1 multiplexer. The 9th leg of this multiplexer comes from the output of the first 8:1 mux of original incoming data (as seen in the Fig. 1 & 2 ). The select of this 9th leg is determined from the bypass select logic. The 8:1 alignment multiplexing with the incoming data is done during the read access of the instruction buffer. The only overhead of this internal bypassing is converting the 8:1 mux to an 9:1 mux. As these...