Effecting a One-Cycle Cache Access in a Pipeline Having Combined D/A Using a BLAT
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26
A base register look-aside table (BLAT) having one entry per architected register is provided to permit an RX instruction to be accomplished in a three-stroke operation in a four-stroke pipeline typically having a two-cycle cache fetch. The BLAT contains the physical cache address of the line that was last referenced and uses the corresponding architected register name for a base designation. In effect, the BLAT permits cache access to be started early.