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Fast Carry Propagating Cmos Full Adder

IP.com Disclosure Number: IPCOM000034049D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26

Publishing Venue

IBM

Related People

Authors:
Nicot, S [+details]

Abstract

The circuit described hereafter has been designed to have a rather high carry propagation time when used in a ripple carry adder. A possible way to implement a Full Adder is to map the following equations into circuits with logic functions. - Sum = (A Xor B) Xor Cin - Cout = (A Xor B).Cin + A.B But this solution gives a rather slow carry propagation when the carry has to ripple from one bit to another. In the present approach, the logic tables have been mapped directly into design with transfer gates.