Central Synchronization Unit for Efficient Chip Testing on the ATE
Publication Date: 2005-Jan-17
The IP.com Prior Art Database
Disclosed is a method that includes a central first-in first-out (FIFO) synchronization circuit in the top hierarchy of a chip. This circuit synchronizes all testability signals to the tester clk domain, which serves to clock the read stage of the production FIFO (PFIFO). Benefits include a solution that reduces costs and is simple to implement.