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Memory Bypass Mechanism for Video Graphics Array Logic Circuitry

IP.com Disclosure Number: IPCOM000034167D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-26

Publishing Venue

IBM

Related People

Authors:
Rackley, DP Thompson, SP [+details]

Abstract

A technique is described whereby video memory operational performance is improved, in personal systems using video graphics, by providing a wider data path to the video memory than was previously provided. A bypass circuit is implemented so as to allow bus masters, with data word sizes greater than eight bits, to go directly to the video memory without having to go through an eight-bit interface circuit. (Image Omitted) The circuitry for the prior art, with no memory bypass, is as shown in Fig. 1. Four memory maps (MM0), (MM1), (MM2) and (MM3) are controlled by the video graphics array (VGA) circuit module via control bus 13.