Browse Prior Art Database

Method for Improved Stress Testing of Performance in a Processor Using a Two-Phase Clock System

IP.com Disclosure Number: IPCOM000034198D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Dick, CJ Jones, L Mercier, SJ Roche, T [+details]

Abstract

In a two-phase clocking scheme, the relative timing of the trailing edge of the first clock pulse, with respect to the leading edge of the second clock pulse, determines many of the critical timings in the system. Prior processor designs required a global change of operating frequency to perform stress testing of machine performance. Logic added to an on-chip clock distribution circuit provides the ability to stress the logic paths on a given chip separately from all other chips. Chip-to-chip paths can be stressed independently, with the stress being applied to a grouping of chips in the system. The following implementation illustrates the method. (Image Omitted) Referring to the critical timing diagram which is drawn for a positive active clock signal (Fig.