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Method for Address Decode for Input/Output Devices

IP.com Disclosure Number: IPCOM000034205D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Eng, RC [+details]

Abstract

This article describes a mechanism for use in a computer system for address decoding for input/output (I/O) device adapter cards utilizing a single programmable array logic device and several logic decoders. In the design of I/O device adapter cards for computer systems, it is necessary to provide hardware to examine the address and control lines of the computer system bus to determine which specific I/O device on the card is being selected. This is commonly referred to as address decode. A conventional method to provide address decode is to use discrete digital logic devices (NAND, AND, NOR, and OR gates) to examine the address and control lines and to indicate when the address of a particular I/O device is present. A newer method involves the use of PAL* (programmable array logic) or a programmable logic array (PLA).