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Weighted Length Minimization Algorithm for Printed Circuit Wiring Disclosure Number: IPCOM000034208D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Kolinck, M Lee, JF Wong, C [+details]


A technique is described whereby an algorithm is implemented, as used in integrated circuit layout compactors and channel routers, so as to provide a minimization of wire length when jogs occur in the routing of long wires. The algorithm applies a weight assignment so as to reduce parasitics and improve the quality of the layout. In layout compaction and channel routing, wire length algorithms typically treat the minimization without the consideration of jogs in the routing. When the algorithm does consider jogs, it is with the assumption that all types of wires are equally important in the minimization. However, a more realistic criterion should be that different types of wires can be given weights as to their importance to the circuitry.