Browse Prior Art Database

High-Performance DRAM REFRESH Mechanism

IP.com Disclosure Number: IPCOM000034212D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Shimizu, S [+details]

Abstract

This article describes a new DRAM refresh mechanism to reduce an overhead for DRAM refreshing. In this mechanism, DRAM memory is refreshed in parallel with the usual read or write access. And hence, the overhead for refreshing is reduced to zero in an ordinal condition of memory usage. A DRAM memory must be refreshed periodically to replace the charge which has leaked away. The overhead for refreshing DRAM chips becomes very critical for a large memory system, since a large DRAM array must be divided into several small sub-arrays and those sub-arrays must be refreshed sequentially because of power dissipation. (Image Omitted) The new DRAM refresh mechanism is shown below, using an example for simplicity. A memory system of 16M byte consisting of 128 chips of 1M bit DRAM is used as modules of 32 DRAMs each.