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Scan Line Algorithm for Layout Compactor of Integrated Circuits Disclosure Number: IPCOM000034218D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Lee, JF [+details]


A technique is described whereby a scan line algorithm provides symbolic layout compactness of integrated circuits to allow dense packing so as to expedite design rule analysis. The algorithm implements a two-step scan line approach for a layout compactor. (Image Omitted) Typically, there are two types of scan line algorithms used for compactors, symbolic oriented and shape oriented. In the symbolic- oriented approach, the layout is organized into groups of symbols which share the same center line where the scan line jumps from one group of objects to another group of objects. In the shape-oriented approach, the layout is viewed as a set of rectilinear masks where the scan line is moved from one mask edge to another mask edge.