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Logging and Retrieving of Error Codes During Power-On Self Test Using BIOS Function Calls

IP.com Disclosure Number: IPCOM000034224D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Bennett, JB Chin, AL Lehman, CT [+details]

Abstract

This article describes a technique for use in a processor system to determine which errors occurred during power-on self test (POST). In some processor systems at run time, programs are unable to determine which errors occurred during POST. In the technique disclosed herein, during POST when an error is detected, it is logged in the extended basic input output system (BIOS) data area. The processor system architecture has eleven bytes allocated in the extended BIOS data area to hold up to five POST error codes and a counter. A BIOS interrupt function is encoded into the system ROM as the interface to store and retrieve the error codes. The BIOS interface is illustrated in the drawing which is a flow chart for the logging of error codes during POST using BIOS function calls.