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Method for Predicting the Performance of Set-Associative Cache Memories

IP.com Disclosure Number: IPCOM000034229D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Natarajan, KS [+details]

Abstract

An analytic method is set forth for predicting the hit-ratio performance of a cache memory organized as a set-associative cache; the method can be used in a tool for fast prediction of cache performance for different cache sizes. The design of cache memories for use in main memory of computer systems can be facilitated by fast and effective tools that can predict the performance for a wide range of cache configuration parameters. Set-associative mapped cache memory organization is commonly used in modern computer systems [1]. Three key parameters that are used to characterize such caches are a) the number of congruence classes (N), b) degree of associativity (K), the number of lines per class, and c) the number of bytes (L) per line. The size of the cache, S, is the product NKL. For our present discussion, let L=1.