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Fast Packet Bus for Microprocessor Systems With Caches

IP.com Disclosure Number: IPCOM000034231D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Butler, ND Larky, SP Parks, TJ [+details]

Abstract

Increased microprocessor performance requires increased processor-to-memory bandwidth. The addition of a cache with a line size greater than one offers the highest processor performance at the cost of still higher bus bandwidth requirements. A fast local bus is defined that allows packetized transfers that both maximize memory subsystem efficiency and minimize processor delay during a cache line reload. In microprocessor systems the processor needs to access memory for both instructions and data. The access time of memory is inversely proportional to the cost of the memory - fast access memory is available at higher cost than slower memory. A frequent solution is to provide a small amount of high cost fast memory and a large amount of lower cost memory. The small, fast memory is called a cache.