Browse Prior Art Database

PROGRAMMABLE PULSE SEQUENCE CONTROL OF DYNAMIC RAMs

IP.com Disclosure Number: IPCOM000034242D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Brewer, JA Dvorak, TJ Stickels, DR [+details]

Abstract

This article describes a circuit arrangement for generation of accurate and repetitive control and refresh sequences to dynamic random access memory (DRAM) arrays utilizing programmable pulse sequence control. DRAMs are generally cost-effective components to use in any large computer memory system. DRAMs need a large amount of control and sequencing logic to insure that specifications, such as refresh, access time, and precharge, are met. This logic usually involves a clock and its support circuitry, several counters or timers, and a large amount of decode or combinational logic. Frequently, a series of cascaded time delays are also used to guarantee the correct sequencing of the DRAM control lines.