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Five-Point General-Purpose Register for Microprocessors

IP.com Disclosure Number: IPCOM000034254D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Chen, CL [+details]

Abstract

A technique is described whereby a five-point general-purpose register (GPR) is provided for microprocessors, so as to increase performance, by enabling three read and two write operations to be performed simultaneously. Described are three unique circuits which make up the GPR. . Five-Port Static Random-Access Memory (RAM) Cell A static RAM cell with a p-channel load is used and consists of a cross-coupled CMOS inverter pair and two sets of five word-line pass- transistors, as shown in Fig. 1. The word-line transistors are connected together by means of 'first' metal lines and arranged in a U-shape around p-channel load devices, so as to minimize the cell area. The bit-lines, both true and complement phases, are connected to a sense amplifier through 'second' metal lines to achieve high-speed sensing.