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Analog CMOS Trench Gated N-Well Log-Linear Current Source Device Disclosure Number: IPCOM000034263D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Voldman, SH [+details]


A semiconductor device is shown which produces a logarithmic increase in current for each volt applied across a trench-substrate surface. The device has many unique applications in the 1-to-8 volt region. A P-diffusion trench structure provides a gate electrode that controls a current mechanism on the trench sidewall. The current collected is at the N-well-to-substrate junction (N-well diffusion). The mechanisms are a thermal generation mechanism and a Zener tunnelling mechanism. Referring to Fig. 1, when a CMOS trench is connected to a P-diffusion inside an N-well which is at the same potential as the trench, i.e., Vwell = VTR, the following equation is valid: IN-well Z IoPe2.