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Method for Calculating a Jump Address in a Microprocessor Disclosure Number: IPCOM000034266D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Ellman, A Rudelis, GH [+details]


By utilizing a 3-way adder in the memory management unit (MMU) of a microprocessor to calculate most jump addresses in one cycle, jump and branch instructions can be processed at a greater rate. Previously fetched instructions are executed in the execution unit (EU) while jumps are executed in the MMU. A block diagram of the bus unit is shown in Fig. 1. A 3-way adder 10 in the MMU is used to sum the instruction pointer address with the jump displacement and the delta queue information. The delta queue logic, as shown in Fig. 2, is contained in the instruction unit (IU) and is updated every cycle to insure that a new jump address can be calculated in one cycle. Unconditional jumps are detected at decode time and their execution occurs in the MMU concurrent with the decoded queue instructions being executed in the execution unit.