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Enhanced Logic Test System Driver Auto Calibration Algorithm

IP.com Disclosure Number: IPCOM000034268D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

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Related People

Gardner, ML [+details]


A new algorithm is shown which results in a reduction in logic test time and enhances tester throughput by automatically calibrating the test system's 1/0 level driver using fewer iterations through the calibration algorithm. A commonly used logic test system's driver auto calibration (DAC) algorithm requires many iterations to achieve a target voltage. Referring to Fig. 1, when a logic test driver is series terminated (usually with a 90-ohm line terminator), good AC characteristics are achieved; however, the applied voltage at the 1 or 0 level DAC does not represent the same voltage seen at the device test pin due to driver offset and a voltage drop across the line terminator.