Browse Prior Art Database

Bipolar/Cmos SRAM Cell

IP.com Disclosure Number: IPCOM000034272D
Original Publication Date: 1989-Jan-01
Included in the Prior Art Database: 2005-Jan-27

Publishing Venue

IBM

Related People

Authors:
Dittrich, MS El-Kareh, B Gravenites, GG Puttlitz, AF [+details]

Abstract

Low-power static random-access memory (SRAM) designs, particularly those using battery back-up, necessitate the use of CMOS in the array. The chip performance can be increased by using bipolar structures in the access path. The unique CMOS process disclosed here utilizes only eleven masking steps to a first level metal and is compatible with bipolar designs. (Image Omitted) Referring to Fig. 1, the common NMOS source 10 and 11 is connected to ground while the common PMOS source 12 and 13 is connected to VH . In conventional designs, the connections necessitate additional wiring paths utilizing one of the metal levels. The disclosed process provides buried layers for these connections, as shown in Figs. 3 and 4, thus reducing the cell size. The main process features are illustrated in Figs. 2, 3 and 4.